1. Field of the Invention
The invention relates to a semiconductor device and a fabricating method thereof, and more particularly to a thin film transistor and a fabricating method thereof.
2. Description of Related Art
Along with the maturation of photoelectrical technology and semiconductor fabrication technology, flat displays have been developed vigorously. Flat displays have gradually replaced the conventional cathode ray tube (CRT) displays and become the mainstream of display products recently for the advantages of low voltage operation, free of radiation scattering, light weight, and compact volume. Generally, liquid crystal displays (LCDs) can be categorized into amorphous silicon thin film transistors (TFT) and low temperature polysilicon TFTs.
Having higher carrier mobility and device stability, low temperature polysilicon TFTs can be widely applied in product design. However, as the development progresses to large-sized panels, low temperature polysilicon TFTs is limited to its fabrication temperature and the specification of the machine, and thus cannot be applied in large-sizes panels. For example, in the fabrication of low temperature polysilicon TFTs, doped regions have to be formed by implantation. Nevertheless, the specification of the conventional implantation machines fails to incorporate the fabrication of large-sized panels to form low temperature polysilicon TFTs. In contrast, the fabrication of amorphous silicon TFTs satisfies the demands for large area production. As a consequence, the combination of the polysilicon fabrication and the amorphous silicon fabrication is proposed for fabricating polysilicon TFTs. For instance, crystallized parts of the polysilicon TFTs are formed by crystallization methods such as the solid phase crystallization (SPC), and the remaining parts are completed in the assembly line of the amorphous silicon TFTs to prevent the use of doping machines. As shown from experiments, the structural properties of the polysilicon TFTs formed by the method aforementioned are affected by the etching process performed to the channel layer, and the device characteristics are evidently affected by the structure of the channel layer.